Analog and Digital Electronics 2024 — MAKAUT · ESC-301 · Mid Sem PYQ with solutions

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Maulana Abul Kalam Azad University of Technology

Solutions

29 answers across 3 groups

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Group AVery Short Answer Type Question · answer any 10 · 1 mark each

  1. 1(i)

    What will be the minimal product-of-sums function described by the K-map given in Fig.

    C \ AB00011110
    011ϕ\phi0
    100ϕ\phi0
    Show answer to question 1(i)Free sample

    Answer: F=A′⋅C′F = A' \cdot C'

    Explanation

    To find the minimal product-of-sums (POS), we group the 0s in the K-map. Zeros are located at cells: (0, 10) →m4\rightarrow m_4, (1, 00) →m1\rightarrow m_1, (1, 01) →m3\rightarrow m_3, (1, 10) →m5\rightarrow m_5. Don't cares (ϕ\phi) are at: (0, 11) →m6\rightarrow m_6, (1, 11) →m7\rightarrow m_7. We can form two quads of zeros:

    • A quad in the bottom row (C=1) covering m1,m3,m7,m5m_1, m_3, m_7, m_5. This gives the sum term C′C'.
    • A quad covering the rightmost two columns (m4,m5,m6,m7m_4, m_5, m_6, m_7). This corresponds to A=1, giving the sum term A′A'. Thus, the minimal POS expression is A′C′A' C'.
  2. 1(ii)

    Arrange the Classes of power amplifier according to their efficiency ( low to high) Class A , Class B , Class C , Class AB

  3. 1(iii)

    What wil be the output of the logic gate in figure given below : [Figure: A NOR gate with one input connected to A and the other connected to ground]

  4. 1(iv)

    In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is: P = Q = "0". If the input condition is changed simultaneously to P = Q = "1", what will be the outputs X and Y now ?

  5. 1(v)

    If the input to the digital circuit (in the figure) consisting of a cascade of 20 XOR-gates is X. What will be the output Y ?

  6. 1(vi)

    The circuit of following figure shows a IC 555 Timer connected as an Astable multivibrator. The value of the capacitor C is 10 nF. Find the values of the resistors RAR_A and RBR_B for a frequency of 10 kHz and a duty cycle of 0.75 for the output voltage.

  7. 1(vii)

    What will be the minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer ?

  8. 1(viii)

    Consider the given circuit. Explain whether , the race around will occur or not [Circuit on Page 2: A level-triggered JK latch implemented with NAND gates. Inputs J=A, K=B and clock Clk]

  9. 1(ix)

    Which A/D converter is used for Hum rejection ?

  10. 1(x)

    The a.c. output power of a Class B push-pull power amplifier is 10 watt. What will be the d.c. input power drawn from power supply when the efficiency of the is maximum .

  11. 1(xi)

    What is octal value of (26)10(2^6)_{10} ?

  12. 1(xii)

    Statement 1: Astable Multivibrator can be used for generating Square Wave. Statement 2: Bistable Multivibrator can be used for storing binary information. Please state whether both the statements are true or false.

Group BShort Answer Type Question · answer any 3 · 5 marks each

  1. 2

    In a JK flip-flop, we have J=Q' and K=1 (see figure). Assuming the flip-flop was intially cleared and then clocked for 6pulses, What will be the sequence at the Q output ?

  2. 3

    Derive the maximum efficiency of a class B amplifier

  3. 4

    Explain the operation of transformer coupled Cass A amplifier

  4. 5

    Find out what will be the modylous of this conter? [Figure: A 2-bit counter using two JK flip-flops. FF0: J0=Q1', K0=1. FF1: J1=Q0, K1=1. Clock connected to both.]

  5. 6

    Design a Full subtractor ( X,Y and Borrow ) with 4 : 1 MUX

Group CLong Answer Type Question · answer any 3 · 15 marks each

  1. 7(a)

    Find the out expression for the Karnaugh Map shown below

    AB \ CD00011110
    000000
    011001
    111011
    100000
    Show answer to question 7(a)5 marks
  2. 7(b)

    Find the out F interms of A and B [Figure: A 2:1 Multiplexer. Input A passes through a NOT gate to MUX input 0. Input A connects directly to MUX input 1. Select line S is connected to B.]

    3 marks
  3. 7(c)

    Find the output expression F for the following Karnaugh Map and realise it with logic gates

    C \ AB00011110
    011
    111
    Show answer to question 7(c)7 marks
  4. 8(a)

    A digital circuit which compares two numbers A3A2A1A0 (A) B3B2B1B0 (B) is shown in figure. Find the pair A , B to get output Y = 0 [Figure: 4 XOR gates. Each XOR takes one bit of A and one bit of B (A3,B3), (A2,B2) etc. All 4 XOR outputs feed into a 4-input NOR gate. The NOR gate output is Y.]

    5 marks
  5. 8(b)

    Consider the multiplexer based logic circuit shown in the figure. Find the Boolean functions is realized by the circuit. [Figure: Two 2:1 MUX cascaded. First MUX: S=S1. I0=W, I1=W passed through NOT gate (W'). Output of first MUX goes to I0 of second MUX, and also through a NOT gate to I1 of second MUX. Second MUX: S=S2. Output is F.]

    5 marks
  6. 8(c)

    A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns. Find the maximum clock frequency that can be used in this counter:

    5 marks
  7. 9(a)

    Find the output Z in terms of X and Y [Figure: 4x1 MUX. Select lines: S1=Y, S0=Gnd. Data Inputs: I3=Y, I2=+5V, I1=X, I0=X. Output=Z]

    8 marks
  8. 9(b)

    A Boolean function F(A,B,C,D) = π(1,5,12,15)\pi(1, 5,12,15) is to be implemented using an 8x1 multiplexer (A is MSB). The inputs ABC are connected to the select inputs S2S1S0S_2 S_1 S_0 of the multiplexer respectively. [Figure on page 4: 8x1 MUX with pins 0-7, Output f(A,B,C,D) and select lines S2=A, S1=B, S0=C] Find the correct inputs to pins 0, 1, 2, 3, 4, 5, 6, 7 in order.

    7 marks
  9. 10(a)

    A 3-bit gray counter is used to control the output of the multiplexer as shown in the figure (A2A_2 is MSB and A0A_0 is LSB). The initial state of the counter is 0002000_2. The output is pulled high. Find the sequence of the output of the circuit [Figure: 3-bit gray counter A2 A1 A0. 4x1 MUX with active low enable E connected to A2. Select lines S0=A1, S1=A0. Data I0=CLK, I1, I2, I3 unconnected. Output has a pull-up resistor to +5V.]

    8 marks
  10. 10(b)

    A 3 line to 8 line decoder, with active low outputs, is used to implement a 3-variable Boolean function as shown in figure: Find the simplified form of Boolean function F(A,B,C) implemented in 'Product of Sum' form. [Figure: 3x8 Decoder. Inputs Z=A0, Y=A1, X=A2. Outputs 0-7 are active low. Outputs 1, 2, 4, 7 feed into a NAND gate to produce F.]

    7 marks
  11. 11(a)

    Digital input signals A, B, C with A as the MSB and C as the LSB are used to realize the Boolean function F = m0 + m2 + m3 + m5 + m7, where mi denotes the ith minterm. In addition, F has a don't care for m1. Find the simplified expression for F

    10 marks
  12. 11(b)

    Find the prime implicants in the sum of products function (X,Y,Z)=∑(2,3,4,5)\sum(2,3,4,5)

    5 marks

About this paper

The MAKAUT Analog and Digital Electronics (ESC-301) 2024 Mid Sem previous year question paper, set in semester 3. Download the verified PDF or read it online, then check your answers against the worked solutions above.

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What is the subject code for Analog and Digital Electronics?

ESC-301 is the MAKAUT subject code for Analog and Digital Electronics.

Which exam is this Analog and Digital Electronics question paper from?

The MAKAUT 2024 Mid Sem exam, semester 3. A student shared it, and it was checked before publishing.

Which branches is this Analog and Digital Electronics paper for?

It's a common paper for 4 B.Tech branches: Computer Science and Engineering, Computer Science and Engineering (Data Science), Information Technology and Computer Science and Engineering (Artificial Intelligence and Machine Learning). Every branch gets the same questions.

Where can I find more ESC-301 question papers?

On the Analog and Digital Electronics subject page, which collects every year's papers along with notes and the syllabus.

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